As more electronic circuits are included on a single die, the power dissipated by a single die continues to increase. In order to keep a single IC (integrated circuit) at a reasonable temperature, many techniques have been used. For example, elaborate cooling fins have been attached to the substrate of ICs. Also, fans have been positioned near a group of IC's to cool them. In some cases, liquids have been used to remove the heat produced by ICs. These solutions can be costly and may require a great deal of space, where space is at a premium. If the power on ICs can be reduced while still achieving higher levels of integration, the cost and area of devices that use ICs may be reduced.
The number of bits contained on a semiconductor memory chip, has, on average, quadrupled every three years. As a result, the power that semiconductor memories consume has increased. Computer systems may use large numbers of stand-alone semiconductor memories. Part of the semiconductor memory used by these computer systems may be held in standby mode for a certain amount of time. The portion of memory that is held in standby is not accessed for data and as result, has lower power requirements than those parts of semiconductor memory that are accessed.
Part of the power used in stand-by mode is created by subthreshold and gate leakage currents in each individual memory cell of the semiconductor memory. Because the amount of memory used in a computer system or as part of a microprocessor chip is increasing, the power, as result of leakage currents in semiconductor memory cells is also increasing. Typically, leakage is proportional to the voltage applied to a memory cell.
Several methods have been used to reduce subthreshold leakage in memory cells. One method increases the Vt of the transistors in the memory cell. Another method increases the thickness of the gate oxide of the transistors in the memory cell. These methods typically require extra processing steps. These extra processing steps increase the cost of an IC. In addition these methods may reduce the speed at which data may be accessed from the memory cells.
Another method for reducing power used by memory cells is to provide a separate lower voltage power supply for memory cells. This method requires a more complex package for an IC and more design effort to physically route another power supply. As result, the cost of a packaged IC typically increases.
There is a need in the art to reduce the power consumed by memory cells. An embodiment of this invention reduces the power used by memory cells without significantly increasing the cost of a packaged IC or without significantly increasing the data access times of the memory cells.